In recent years, with the advancement of digital technologies, higher functionality of electronic hardware such as portable information devices and information home appliances have been provided. With the progress of the higher functionality of the electronic hardware, miniaturization and an increase in a speed of semiconductor elements for use with them have been making rapid progress. Among them, applications of a nonvolatile memory element using a ferroelectric film or the like which is capable of writing and reading at a high speed with low electric consumption, as a material for a memory portion, have spread at a rapid pace.
Furthermore, since the nonvolatile memory element using a resistance variable layer as a material for a memory portion can constitute a memory element only by using a resistance variable element, further miniaturization, an increase in a speed, and lower electric power consumption of the nonvolatile memory element have been expected.
When using the resistance variable layer as the material for the memory portion, it is required that its resistance value change from a high-resistance value to a low-resistance value or from the low-resistance value to the high-resistance value by applying electric pulses such that these two values are clearly distinguished and the resistance value stably change. For the purpose of such stabilization of retention characteristic and miniaturization of the memory element, structures of the resistance variable layer have been disclosed.
FIG. 21 shows an example of a conventional memory element, in which a memory cell is formed by a resistance variable element having two storing layers which are sandwiched between two electrodes and whose resistance values change reversibly (see patent document 1, for example).
As shown in FIG. 21, the memory element consists of a number of resistance variable elements 10 forming memory cells and arranged in an array form. Each resistance variable element 10 has a structure in which a high-resistance layer 2 and an ion source layer 3 whose resistance is lower than a resistance of the high-resistance layer 2 are sandwiched between a lower electrode 1 and an upper electrode 4. The high-resistance layer 2 and the ion source layer 3 form a storing layer. The storing layer enables data to be stored in the resistance variable element 10 in each memory cell.
The resistance variable elements 10 are respectively disposed above MOS transistors 18 provided on a semiconductor substrate 11. The MOS transistor 18 includes source/drain regions 13 formed in a region separated by an isolating layer 12 inside the semiconductor substrate 11 and a gate electrode 14. The gate electrode 14 also serves as a word line which is one address wire of the memory element.
One of the source/drain regions 13 of the MOS transistor 18 is electrically connected to the lower electrode 1 of the resistance variable element 10 via a plug layer 15, a metal wire layer 16, and a plug layer 17.
The other of the source/drain regions 13 of the MOS transistor 18 is connected to the metal wire layer 16 via the plug layer 15. The metal wire layer 16 is connected to a bit line which is the other address wire of the memory element.
By applying electric potentials of different polarities between the lower electrode 1 and the upper electrode 4 of the resistance variable element 10 configured as described above, ion source of the ion source layer 3 forming the storing layer is caused to migrate to the high-resistance layer 2 or the ion source is caused to migrate from the high-resistance layer 2 to the upper electrode 4. Thereby, the resistance value of the resistance variable element 10 transitions from a value of a high-resistance state to a value of a low-resistance state, or from a value of the low-resistance state to a value of the high-resistance state, so that data is stored.
A memory element is also disclosed, in which a resistance variable layer material sandwiched between an upper electrode and a lower electrode is formed by a first electric pulse varying resistance layer having a polycrystalline structure and a second electric pulse varying resistance layer having a nano crystal structure or an amorphous structure. The resistance layer formed of this memory resistance material is controlled so that its resistance value is caused to change according to a voltage and pulse width of electric pulses applied, thereby operating as a resistance variable element (see, for example, patent document 2).    Patent document 1: Japanese Laid-Open Patent Application Publication No. 2006-40946    Patent document 2: Japanese Laid-Open Patent Application Publication No. 2004-349689